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Teradyne FPGA Design Verification Engineer in North Reading, Massachusetts

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne ( companies deliver manufacturing automation across industries and applications around the world!

Organization & Role

The Teradyne Hardware Engineering team is looking for a highly-motivated, energetic, technically driven Semiconductor Engineer to focus on digital FPGA design verification for products within the Semiconductor Test division. Development occurs in a dynamic and challenging multi-site development environment. This individual will report directly to the Hardware Engineering Manager.


Do functional verification cycle of Next Generation Automatic Test Equipment (ATE) instrument design verification projects by performing the following duties:

  1. Develop verification plan/strategy to cover different verification aspects:
  • Block level, sub-system-level, and system-level test strategy.

  • Reference model and data checker for the design.

  • Feature list based on design specification.

    1. Develop test environment and test coverage using Constrained Random in System Verilog and UVM/Assertion-Based methodology.
  • Create test environment using different verification IPs (VIP): PCIe, Ethernet AXI, and DDR.

  • Create UVM components, APIs, and UVM test sequences.

  • Close functional and code coverage

Basic Qualifications & Skills

Have 2+ years of work experience in the following:

⦁ Proprietary interfaces (IP) and simulation tools.

⦁ Digital design verification.

⦁ Block, sub system and system level verification concepts

⦁ Some IP Protocol knowledge (e.g SPI, AXI, and DDR)

⦁ Universal Verification Methodology (UVM) based coverage driven verification methodology.

⦁ System Verilog Assertion-Based methodology.

⦁ Good at Object Oriented Programming (OOP) and code-reuse


⦁ Bachelor’s degree in Engineering (Electronics, Electrical Engineering, or related field).

⦁ 2+ years of experience in digital design verification.


Current openings may involve access to export controlled technology and may be subject to export licensing requirements prior to employment. ATTENTION APPLICANTS WITH DISABILITIES: If you’re unable to access our on-line application due to a disability you may visit one of our locations or our Corporate Office at 600 Riverpark Drive, North Reading, MA and request a paper application form. In addition, you may also contact the HR Service Center at 978-370-3041 or contact them at for additional assistance. LitePoint, a Teradyne Company is an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, age, disability status, protected veteran status, or any other characteristic protected by law. We are a VEVRAA Federal Contractor.