Raytheon Manager III – PCS Firmware Section Manager in Marlborough, Massachusetts

Job Description: Are you interested in joining a dynamic, inclusive, and growing professional organization? Our primary focus is to design and provide Mission capable hardware to our customer. Our mission is to develop innovative designs using the latest proven technology in a collaborative environment which is characterized by respect for the individual, problem solving in a team setting, consensus oriented solutions, and results based recognition. Supporting this mission are teams providing domain expertise and creative solutions in Integrated Communication Systems (ICS) covering encryption devices, radios, transponders, satellite and network communications. Manager III – PCS Firmware Section Manager We are looking for an experienced senior level FPGA designer with management experience to join our team. The successful candidate will function as the Section Manager of a group of 15 FPGA design and verification engineers contributing to program staffing and continuously improving our FPGA Design and Verification processes and associated tools and technologies. Responsibilities of this position include: Provide functional leadership and management of 15 design and verification engineers, work assignments and resource allocation, career development and mentoring. Responsible for developing best practices in FPGA Design and Verification processes such as High Level Synthesis (HLS) and Universal Verification Methodology (UVM). Encourage and foster innovation and technology insertion into our product lines such as ARM-based SoC, DSP-based processing, Security, NVMe, and other relevant technologies. Responsible for execution of all FPGA work scope on all programs. Program firmware lead will be assigned for day to day execution. Section Manager will ensure estimates provided at proposal bid response is executable, risk and opportunities are identified and provided to program manager. Section Manager is responsible for successful program start up ensuring that the scope and financial baseline being provided to the program, any deltas from the time of proposal are identified as a risk, opportunity or removed from baseline ensuring the program tasks are executable within cost and schedule. Section Manager will review program performance progress monthly by reviewing the latest revised estimates (LREs) and Quarterly EACs. Section Manager will review or provide Estimates at Completion (EACs) Participate in milestone design reviews. SM will align resources such as Product line Subject Matter Experts and Independent Reviewers to support the design reviews. Ensure the Section is properly using the established processes Reviewing program execution and capturing department metric collection Participate in Business capture activities, bid package generation, and Basis of Estimates (BoE). Develop relationships with Program Managers and other Section Managers to ensure steady work assignments for direct reports. Perform as Hiring manager to increase talent base. Serve as a role model for behavior and conduct. Required Skills: A minimum of 8 years professional engineering experience as a senior FPGA Designer and a minimum of 2 years as a manager Extensive experience in developing optimal FPGA architectures based on high level requirements. Experience in project team leadership, including technical, budget, staffing, and schedule management Experience with FPGA and CPLD devices and development tools from Xilinx, Altera, Microsemi and Lattice. Proficiency with functional verification test flow using VHDL with assertions. Knowledge of Universal Verification Methodology (UVM) is highly desirable. Proficiency with Questa Sim for functional verification Experience incorporating third party IPs into FPGA designs, including PCIe and high speed Ethernet stack. Experience working independently in a complex system integration environment, verifying requirements and identifying and correcting defects. Passion for coaching people, mentoring and encouraging career development Demonstrated task ownership and accountability Possess, or able to obtain, Secret security clearance and COMSEC clearance. Desired Skills: Experience with satellite communications systems, including familiarity with security aspects of protected satellite communications systems Familiarity with security aspects of protected satellite communications systems. Experience using DOORs tool for requirements capture and flow-down. Experience in cost estimation and metric collection Advanced firmware waveform generation techniques Been involved with a UVM-based verification project Familiarity with code coverage tools for evaluating test coverage. Familiarity with version control tools such as Clearcase or GitHub Experience with Scrum / Agile execution and planning Good communication and presentation skills. Six Sigma/process improvement experience. Required Education: Bachelor’s degree in Electrical Engineering or Computer Science Desired Education: Master’s Degree in Electrical Engineering or Computer Science 130905

Raytheon is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, sex, sexual orientation, gender identity, national origin, disability, or protected Veteran status.