Draper Senior FPGA Design Engineer in Cambridge, Massachusetts
Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 1,800 employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.
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We are seeking a talented senior engineer to join the digital design team at Draper. The successful candidate will contribute to FPGA development including design, synthesis, verification, validation, test & support. Candidate must have experience using high level design, simulation and verification tools and be familiar with process flows supporting design and verification for digital FPGA efforts. Applicant should also be familiar with embedded software development for FPGA SoCs. Preference will be given to candidates with an understanding of hardware security, signal or image processing, filter design and algorithm implementation in hardware. Direct experience with embedded FPGA design is required.
BSEE with 6 years relevant experience
Fluent in Verilog/VHDL
Understanding of networking (specifically Ethernet/IP) layered models and protocols
Implementation of FPGA functions to accelerate SW (checksum engines, packet parsing, etc.)
Ability to debug designs simulated in a UVM environment
Capability to learn Libero tools, PolarFire (SoC) devices, and IP
Experience with joint design/debug with embedded software
Experience debugging FPGA fabric designs with embedded processor software on HW
Capability for evaluating trade space for adding new features to FPGA fabric and/or software (knows strengths of each technology and can optimize based on requirements)
Experience with design closure including timing, power and area for SWaP constrained designs
Familiarity with high speed interfaces (10Gbit Ethernet, PCIe, DDR4, LVDS, etc)
Experience with Linux and scripting languages
Strong analysis and problem solving skills
MSEE with 6 years relevant experience
Experience with 10GB Ethernet and IP id HDL designs
Understanding of higher layer protocols (TCP, UDP, etc.)
UVM skills (Test and/or Test Bench development)
Microchip Libero/PolarFire development
Experience with Microchip (Microsemi/Actel) IP
Experience with embedded processors within FPGAs
Experience with Xilinx Vivado design tools and Petalinux
Experience with Matlab/Simulink
Experience working with PCB designers
Active US secret/TS clearance strongly preferred
- Applicants selected for this position will be required to obtain and maintain a US government security clearance which requires proof of US citizenship.
** Draper has implemented a mandatory COVID-19 vaccination requirement for all Draper employees. This will be a condition of employment to work at Draper.
External Company Name: The Charles Stark Draper Laboratory Inc