Draper Senior Digital Electronics Design Engineer in Cambridge, Massachusetts
Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 1,700 employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.
Our work is very important to us, but so is our life outside of work. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. If this specific job opportunity and the chance to work at a nationally renowned R&D innovation company appeals to you, apply now www.draper.com/careers.
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Draper is committed to creating a diverse environment and is proud to be an affirmative action and equal opportunity employer. We understand the value of diversity and its impact on a high-performance culture. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, gender identity, national origin, veteran status, or genetic information.
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We are seeking a talented engineer to join the digital IC design team at Draper. The successful candidate will contribute to ASIC and FPGA development including design, synthesis, verification, validation, test & support. Candidate must have experience using high level design, simulation and verification tools and be familiar with process flows supporting design and verification for digital ASIC / FPGA efforts. Proficiency with ASIC and SoC design and development process flows is preferred. Preference will be given to candidates with an understanding of hardware security, signal or image processing, filter design and algorithm implementation in hardware.
Requirements capture and derivation
Architecture definition and performance analysis
Integration of third-party IP
Design implementation using SystemVerilog, Verilog or VHDL
Familiarity with CDC, LEC and formal techniques
Leading design and architecture teams
Top-level chip integration
PhD or MSEE+6 preferred
Strong analysis and problem solving skills
Fluent in SystemVerilog/Verilog/VHDL
Fluent in Cadence or equivalent Digital ASIC Tool Suite, e.g., Genus, Innovus, Tempus, Voltus, etc.
Experience with high-level design, simulation, and verification tools
Experience with scripting languages Python/PERL and regular expressions
Ability to acquire and maintain a security clearance
Experience with Linux/UNIX OS, piping, batching, etc.
Experience with SRAM compilers and architecture tradespace
Familiarity with memory design for SRAM, DRAM, and NVRAM
Familiarity with SOC tradespace including processor selection, memory and bus implementation and architecture
Experience with emulation
Familiarity with hardware security, e.g., encryption, key management, TRNG/DRNG, PUFs, root-of-trust, design obfuscation, etc.
Active security clearance
Applicants selected for this position will be required to obtain and maintain a U.S. Security Clearance.
External Company Name: The Charles Stark Draper Laboratory Inc