Job Information
Accenture Silicon DFT Engineer in Boston, Massachusetts
We Are:
The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
You Are:
An experienced DFT Engineer
The Work:
Work with the Silicon teams to document the DFT specifications and define the requirements
Develop and implement DFT architecture and infrastructure
Develop and drive execution of enhanced DFX (DFT/Design-For-Debug) methodologies, with increased focus on debug support
Work with the DV team to verify DFT implementations
Generate structural test vectors, analyze and improve coverage/test time/test cost
Work with designers on STA, physical, power and logical issues impacting DFT
Work with test engineers to bring up test vectors on silicon
Work with lab bring-up teams to bring up test vectors in the lab environment
Manage schedules and support internal and external cross-functional/cross-organizational engineering efforts
Here’s what you need:
A minimum of two years of experience with Hardware Design-For-Test (DFT) engineering including
A minimum of two years of experience in silicon design and/or verification
Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
Bonus points if:
Developing DFT specifications
Industry standard DFT and design tools
Debugging ATPG/MBIST patterns
STA constraints and their interaction with DFT
Experience with Root Cause Analysis
IP / Top Scan insertion (all EDA solutions)
IP / Top Mbist insertion (all EDA solutions)
Scripting languages TCL/Perl/Python
Experience with Synopsys DFT tools (Tetramax, DFT compiler, BSD compiler, Formality, Spyglass)
Experience with JTAG and IEEE standards 1149.1 and 1149.6.
Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in California, Colorado, District of Columbia, Maryland, New York or Washington as set forth below.We accept applications on an on-going basis and there is no fixed deadline to apply.
Information on benefits is here. (https://www.accenture.com/us-en/careers/local/total-rewards)
Role Location Annual Salary Range
California $63,200 to $188,600
Colorado $63,200 to $163,000
District of Columbia $67,300 to $173,500
New York $58,500 to $188,600
Maryland $58,500 to $150,900
Washington $67,300 to $173,500
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