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Intel Full Chip Engineer in Boston, Massachusetts

Job Description

Come build a future with us! Intel is seeking highly qualified candidates to join our System Solutions Engineering (SSE) team, part of the Programmable Solutions Group (PSG). PSG continues to deliver industry-leading (FPGA) Field-Programmable Gate Array , solutions to customers and our team is responsible for the technical enablement of customer applications in embedded and defense segments. We aim to be domain experts while bringing together applicational needs and the future of FPGA technology.

Do you love a technical challenge? Are you a problem solver that loves team collaboration and helping customers? Are you a visionary that challenges the status quo? Intel Federal Labs and Intel's SSE team is searching for talented and innovative SoC Design Engineers to participate in collaboratively focused research, design, and development to advance novel and exciting solutions to government facing problems leveraging Intel's latest and high-performance tools.

As a Full Chip Engineer, you will be developing timing and power methodologies and executing full-chip timing for Intel's Programmable Solutions Group's next generation product lines in the world's most advanced process technologies. This will be a fast-paced dynamic environment where you will be part of a high-performance design team working toward next generation FPGA products. You will work in a hands-on capacity performing full chip timing and power analysis. You will utilize your extensive design experience and interpersonal skills to efficiently solve technical issues, drive continuous improvement, negotiate, and clearly communicate technical trade-offs with a diverse cross-functional and multi-site team. Experienced to work to aggressive schedules as part of a team and independently.

Your role will include, but not limited to:

  • Design and Architecture understanding.

  • Interaction with Front End and Back End teams, clocking and constraints development.

  • Understanding extraction issues, design margins, timing signoff and quality checks.

  • Collaborate with cross-functional teams to define system level power optimization solutions, provide power targets to design teams, and commit product power to meet business goals

  • Be part of debug and troubleshooting for a wide variety of tasks up to and including difficult, critical design issues and proactive intervention

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Qualifications

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field plus 9 or more years of industry work experience, or

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of work experience

Minimum Required Qualifications:

8+ years of relevant experience should include:

  • Experience in SoC development

  • Experience with advanced process nodes (e.g. 32nm and below).

  • Industry standard timing formats such as Liberty, Verilog, and Design Constraints (SDC).

  • Static Timing Analysis (STA) / Correlating STA results with Spice.

  • Timing modeling and library QA.

  • Power analysis tools such as Primetime-PX, Redhawk, Power Artist and Spice

  • Script writing for design automation in one or more of the following languages (Python, Perl, or TCL).

  • Silicon modeling concepts (e.g. AOCV, POCV).

Additional Preferred Qualifications:

  • 10+ years of SoC Development / Timing Lead Experience

  • Experience in the completion of several complex multi voltage domain

  • Experience in power model generation and low power strategy

  • Experience with common modes of operation, including functional and DFT, for use in constraint review and management.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Covid Statement

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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