Massachusetts Green Jobs

Design Verification Engineer

Boston,Massachusetts,United States

Hardware

• Knowledge of System Verilog test-bench language and UVM

• Proven experience developing scalable and portable test-benches

• Proven experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations

• Experience with mixed signal verification methodology

• In lieu of UVM knowledge, C/C++ expert knowledge

• Significant experience with DDR PHY/Controller and/or High Speed SerDes

• Deep knowledge of one of the scripting languages: Python, Perl, TCL

• Knowledge of formal verification methodology a plus

• Knowledge of UPF definitely a plus

Description

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal designs.

Education & Experience

BSEE and MSEE degrees preferred.

Additional Requirements

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